The minimum dimension that a given photolithography process can resolve is alternatively called the minimum feature-size or the critical dimension. The feature-size is a parameter of interest as reductions in the feature-size tend to improve speed performance of the IC. The feature-size of a printed integrated circuit (IC) is not uniform. The printing process results in slight variation of the feature-size from lot-to-lot, from wafer-to wafer, and from device to device within each wafer. As a result, programmable ICs, such as field programmable gate arrays (FPGAs) may experience variations in static power and circuit delay due to variations in the manufacturing process.
Switching speed is not uniform throughout a particular die or from die-to-die. Some manufacturing variations may consistently result in circuit elements in different regions of a die having different switching speeds. These types of variations are referred to as systematic variations. Other manufacturing variations are unpredictable and are characterized as random variations. Random variations may cause variation between dies for a particular location. Random variations may be due to lithography, masking or some other process required in the manufacturing of the integrated circuit devices.
In integrated circuit design, it is often important to synchronize timing in which signals are received by different components. For example, a long signal path between a digital clock manager and data load can cause clock delay, and the signal path may require adjustment in order to synchronize input setup and hold times and provide proper data transfer. Delay circuits are often used to perform this adjustment.
Due to variations in switching speed, two programmable delay circuits on a particular die of a programmable IC may not provide precisely the same phase shift. As the speed of ICs is increased and input setup and hold time windows decrease, a higher degree of accuracy is required for delay circuitry. In order to allow developers to simulate and test circuit designs on target devices using precise propagation timing prior to circuit realization, many programmable IC vendors measure switching speed of several printed devices of a product design to verify correct operation and/or determine accuracy that can be guaranteed to designers. The presence of process variations degrades accuracy and/or operational speed that can be guaranteed to customers.
Automated test equipment (ATE) is often utilized to test the performance of manufactured programmable IC dies in a production environment. ATE may be used to directly measure various individual circuits of an IC in the production environment. In another approach, built-in self-test (BIST) circuits may be implemented to internally test delay circuits by specially configuring a programmable device and measuring the propagation delay related to such a device without using an ATE to directly measure the delay. One BIST implementation configures programmable logic to implement a ring oscillator and a counter to count cycles of the ring oscillator. The counter is configured to provide the ATE with the count of the oscillator's cycles, which can be used to determine the propagation delay of the tested delay circuit under test.
These methods for measuring delay time on the automated test equipment (ATE) are not practical because each delay circuit under test must be measured individually making overall testing time prohibitively long.
One or more embodiments of the present invention may address one or more of the above issues.